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INTRODUCTION 1.1 Background Nowadays, data rates on serial interfaces are increasing rapidly as the technology continuing to advance. CONCLUTION AND FUTURE WORK References viД§ CHAPTER 1. HSPICE MEASUREMENTS AND ANALYSIS Overview HSPICE Simulation Measurement and analysis CHAPTER 6. SERDES CIRCUIT DESIGN TUTORIAL Overview Schematic Editor Creating library Creating schematic cell view Instantiating symbols Creating test bench Extracting HSPICE Netlist vД¦ CHAPTER 5. HIGH SPEED SERDES ARCHITECTURE AND DESIGN Overview Serializer D latch design Multiplexer design CHAPTER 4.

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2 CHAPTER 2.FUNDAMENTALS OF HIGH SPEED SERDES Overview Data transmission Parallel data transfer Serial data transfer High speed SerDes Serializer/ Deserializer blocks Equalizer Clock and data recovery (CDR) Differential driver and receiver Phase locked loop (PLL). Many thanks to my research group colleagues and friends, Thomas Comberiate, Xu chen, Drew Newell, Si Win and Karan Bhagat, for their swift assistance and many valuable discussions during the course of the research. I would like to give special thanks to Rishi Ratan, Da Wei and Jin Lei, for their immense help and support on this project. Working under his supervision has been one of the most enriching experiences of my life.

I thank him for all his attention, encouragement, guidance and support during every stage of my research project. Schutt-AinГ©, for providing me with the opportunity to work in this interesting topic and research in the field of high speed circuit modeling and design. iiiД¤ ACKNOWLEDGMENTS First and foremost, I would like to express my sincere gratitude to my adviser, Professor JosГ© E. To my coworkers, for their advice and assistance. To my adviser, for his attention, encouragement, guidance and support.

iiДЈ To my family, for their love and support. Fundamental concepts and major components of SerDes are covered, as well as the design flow of a Serializer from unit block design in Cadence Virtuoso to simulation in HSPICE, using a 45nm CMOS process. As a result, this thesis serves as an introduction to SerDes for beginners as well as a tutorial of mixed-signal integrated circuit design, using an example of a Serializer circuit. Designing a robust, lower power SerDes that functions properly at high speed is very challenging and requires knowledge from several different areas.

SerDes is very beneficial because it solves the problems of many traditional parallel data links and reduces the number of I/O pins and cost for connectors and cables. A Serializer/Deserializer (SerDes) is such a device that takes the parallel data link input and condenses it into fewer lines of serial stream which would then deserialized and output as the original recovered parallel data. Serial I/O has the advantage of faster speed, less interference between adjacent links, fewer pin counts and thus lower packaging costs. As integrated circuits (IC) become smaller size and faster speed, traditional parallel communication is not suitable due to cross-talk, data-skew, and other problems related to electronic packaging and signal integrity. Schutt-AinГ©Дў ABSTRACT Input/output (I/O) has always played an important part in modern high speed applications. 1 HIGH SPEED CMOS SERDES DESIGN AND SIMULATION USING CADENCE VIRTUOSO AND HSPICE BY JERRY YANG THESIS Submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Electrical and Computer Engineering in the College of Engineering of the University of Illinois at Urbana-Champaign, 2013 Urbana, Illinois Adviser: Professor JosГ© E.